A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 µm CMOS

Volume 2, Issue 2, November 2014, Pages 1-10

mohsen dashtbayazi; Mohammad Taherzadeh Sani; Samaneh Babayan Mashhadi; Ehsan Rahiminejad

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